Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to microprocessors for computer systems. More specifically, the present invention relates to writing information to address and data buses by a microprocessor in a computer system. More specifically still, the invention relates to reducing ground bounce during write operations by a microprocessor.
2. Background of the Invention
Computer systems generally comprise many components, but the heart of any computer system is the microprocessor or central processing unit. Early computer systems may have had a single microprocessor that was responsible for performing instructions and doing calculations as commanded by software operating in the system. As computer software technology advances, computer systems may comprise many microprocessors with varying degrees of computing capability. Some computer systems may have parallel processors to ease the processing load on any one microprocessor. Other computer systems may distribute microprocessors throughout the system with each dedicated to particular functions, for example, there may be a dedicated microprocessor to operate an array of storage devices for the computer system.
In having the ability to execute programs and perform calculations, vast amount of information must be transferred to and written from any particular microprocessor. Microprocessors typically write information from over a plurality of communication buses.
While microprocessors generally have some limited serial communication capabilities, the bulk of microprocessor data communication occurs over parallel communication buses. Using a parallel bus, significant amounts of information exchange between devices in each transfer clock period. For example, an address bus may have fifteen address signal lines coupling the microprocessor to a device with which the microprocessor wishes to communicate. By selectively driving this plurality of address data lines high or low, the microprocessor communicates an address relevant to a write operation. All these exemplary address lines in a parallel scheme transition simultaneously. That is, the microprocessor drives each of these plurality of address signal lines to a high or low state at the same time.
Likewise, data transfer in a parallel bus scheme involves driving a plurality of data signal lines to a high or low state to represent binary information. A data bus could be, for example, 64 data lines wide with the high or low state of each data line representing one bit of information. If a byte represents 8 bits of information, it is clearly seen that a 64 bit wide data bus has the capability of transferring 8 bytes of information in a parallel fashion. Just like the address lines described above, when a microprocessor transfers data across the data bus, the microprocessor places eight bytes of information, that is 64 bits, onto the data lines. The microprocessor accomplishes this task by driving the data lines high or low to represent bits of information. The microprocessor drives these lines simultaneously to facilitate the parallel transfer of information. Thus, for a single parallel exchange of information, a microprocessor may have to drive as many as 79 address and data lines simultaneously. Systems with large cache may require more address lines, e.g. 20. Moreover, server systems may have as many as 512 data lines. The number of data lines a microprocessor may have to drive increases with the addition of clock forwarding for groups of address and data lines as well as error correction lines used in error correction coding schemes.
While many types of bus architectures exist, a common bus architecture of the prior art is the open drain bus architecture. In a bus having an open drain architecture, each address and data signal line attaches to a high voltage through a pull up resister. When the address and/or data bus lines are not in use, the pull up resister pulls the voltage on each line to a high level. When a microprocessor writes information to the address and data lines, the microprocessor selectively leaves the bus in a high voltage condition, to indicate a first state, or pulls the bus down to a low voltage condition, to indicate a second state. In this way, devices writing to buses having an open drain architecture need not source current to charge the bus transmission lines associated with each address and data signal line; rather, the writing device need only sink or drain the current from the address and bus signal lines. While this technique may solve problems related to sourcing current for write operations, new problems arise with respect to sinking current by a writing device.
Resistance and inductance are generally parasite in the design of electric circuits. One of these circumstances is electrically coupling various electronic devices in a modular type computer system. Every location where a detachable electrical connection is made has some inherent resistance and inductance. The resistance element may be attributable to the physical coupling between two electrical conductors. The inductance element may be attributable to other conductive traces located in close physical proximity to the electrical connection at issue. Regardless of the source of the resistance and inductance, these electrical parameters cause undesirable voltages to develop across electrical connectors.
All the current drained to ground or common by the microprocessor must pass through the electrical connector that couples the microprocessor to the motherboard. As the microprocessor simultaneously drives address and data lines by sinking current, there is marked increase in current flow through the ground or common connector associated with this current sinking operation. The resistive element creates a voltage directly proportional to the current flow through the connector. However, the inductive element of the electrical connector creates a voltage that increases with the rate of change current through the electrical connector. Thus, in the instant in time when the microprocessor simultaneously drives all of its address and data signal lines, significant parasitic voltages are created across the electrical connector. Because of these parasitic voltages across the ground or common connector, the operating voltage of the microprocessor drops. This phenomenon is known as ground bounce. If the parasitic voltage across the electrical connector becomes sufficiently high, and therefore the operating voltage seen by the microprocessor becomes sufficiently low, operation of the microprocessor may be impaired.
Prior art devices address this phenomena of ground bounce by having multiple ground or common connectors through which to sink current during write operations by the microprocessor. While this technique may have helped the ground bounce phenomenon by reducing resistance and inductance, those effects are still felt in current microprocessor design technology.
Despite the desirability of reducing ground bounce during write operations of a microprocessor, no suitable system has been developed.
The problems noted above are solved in large part by a technique and related circuit which delays driving of selected address and data signal lines within a clock period of the core frequency clock. Delaying the sinking of currents across the ground connector reduces the voltage created associated with the parasitic inductance of a physical connector. More specifically, the plurality of address and data signal lines associated with a write by a microprocessor are grouped into three transmission groups. A first transmission group preferably comprises only the address signal lines. The microprocessor preferably asserts the address signal lines without delay inasmuch as the receiving device, most likely a bridge circuit, needs the address lines as an indication of what to do with the associated data. The data signal lines are preferably grouped into two further transmission groups. The microprocessor delays assertion of a first of these two transmission groups by half a clock period of the core frequency clock. That is, the microprocessor delays the sinking of current of any of the data signal lines in the second transmission group by half a clock period of the core frequency clock. Further, the microprocessor preferably delays by an entire period of the core frequency clock assertion of the data signal lines associated with the third transmission group.
In this way, the change in current flow through any particular ground connector is distributed over a period of time being the period of one complete clock signal of the core frequency clock. Thus, voltage build up across the connector associated with the parasitic inductive element is reduced because the change in current flow associated with a particular write operation is spread over an entire clock period of the core frequency clock rather than having the microprocessor sink all the current associated with all the address and data signal lines at one time. This reduces the voltage build up across the ground or common connectors which therefore reduces ground bounce.